Conventional semiconductor devices such as integrated circuits (IC) generally comprise a semiconductor substrate, usually a silicon substrate, and a plurality of conductive material layers separated by insulating material layers. Conductive material layers, or interconnects, form the wiring network of the integrated circuit. Each conductor in the wiring network is isolated from the neighboring conductors by the insulating layers, also known as interlayer dielectrics. One dielectric material that is commonly used in silicon integrated circuits is silicon dioxide, although there is now a trend to replace at least some of the standard dense silicon dioxide material in IC structures with low-k dielectric materials such as organic, inorganic, spin-on and CVD candidates.
Conventionally, IC interconnects are formed by filling a conductor such as copper in features or cavities etched into the dielectric interlayers by a metallization process. Copper is becoming the preferred conductor for interconnect applications because of its low electrical resistance and good electromigration property. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using features such as vias or contacts. In a typical interconnect fabrication process; first an insulating layer is formed on the semiconductor substrate, patterning and etching processes are then performed to form features or cavities such as trenches, vias, and pads etc., in the insulating layer. Then, copper is electroplated to fill all the features. In such electroplating processes, the wafer is placed on a wafer carrier and a cathodic (−) voltage with respect to an electrode is applied to the wafer surface while a deposition electrolyte wets both the wafer surface and the electrode.
Once the plating is over, a material removal step such as a chemical mechanical polishing (CMP) process step is conducted to remove the excess copper layer, which is also called copper overburden, from the top surfaces (also called the field region) of the workpiece leaving copper only in the features. An additional material removal step is then employed to remove the other conductive layers such as the barrier/glue layers that are on the field region. Fabrication in this manner results in copper deposits within features that are physically as well as electrically isolated from each other. Another important material removal technique, especially for wafers with low-k dielectrics, is the electrochemical polishing (electropolishing) or electrochemical etching process. In electropolishing, an anodic voltage is applied to the wafer surface with respect to a cathodic electrode in an electropolishing electrolyte. Excess conductor, such as overburden copper is removed without physically touching and stressing the interconnect structure. It is possible to perform electropolishing on a wafer surface while physically touching the surface with a pad material. Such techniques are called electrochemical mechanical polishing or etching methods.
Some of the adverse effects of conventional material removal technologies may be minimized or overcome by employing a planar deposition approach that has the ability to provide layers of planar conductive material on the workpiece surface, as well as planar removal processes. These planar deposition and removal processes also have application in thru-resist processes employed in IC packaging. In these applications plating is performed into holes opened in resist layers onto seed films exposed on the bottom of each hole or opening.
One technique used for planar deposition and removal of materials is collectively referred to as Electrochemical Mechanical Processing (ECMPR), which term is used to include Electrochemical Mechanical Deposition (ECMD) processes as well as Electrochemical Mechanical polishing (ECMP) which is also called Electrochemical Mechanical Etching (ECME). It should be noted that in general both ECMD and ECMP processes are referred to as electrochemical mechanical processing (ECMPR) since both involve electrochemical processes and physical touching to, or mechanical action on the workpiece surface. All electrochemical techniques for material deposition and removal may be referred to as “electrotreatment.”
In one aspect of an ECMPR method, a workpiece-surface-influencing-device (WSID) such as a mask, pad or a sweeper is used during at least a portion of the electrotreatment process when there is physical contact or close proximity and relative motion between the workpiece surface and the WSID. Descriptions of various planar deposition and planar etching methods and apparatus can be found in the following patents and pending applications, all commonly owned by the assignee of the present invention. U.S. Pat. No. 6,176,992 entitled “Method and Apparatus for Electrochemical Mechanical Deposition.” U.S. Pat. No. 6,534,116 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” filed on Dec. 18, 2001, and patent application Ser. No. 09/961,193 filed on Sep. 20, 2001, entitled “Plating Method and Apparatus for Controlling Deposition on Predetermined Portions of a Workpiece”. These methods can deposit metals in and over cavity sections on a workpiece in a planar manner. They also have the capability of yielding novel structures with excess amount of metals over the features irrespective of their size, if desired.
In ECMD methods, the surface of the workpiece is wetted by the electrolyte and is rendered cathodic with respect to an electrode, which is also wetted by the electrolyte. During ECMD, the wafer surface is pushed against or in close proximity to the surface of the WSID or vice versa when relative motion between the surface of the workpiece and the WSID results in sweeping of the workpiece surface. Planar deposition is achieved due to this sweeping action as described in the above-cited patent applications.
In ECMP methods, the surface of the workpiece is wetted by the electropolishing electrolyte or etching solution, but the polarity of the applied voltage is reversed, thus rendering the workpiece surface more anodic compared to the electrode. A WSID touches the surface during removal of the layer from the workpiece surface.
Very thin planar films can be obtained by first depositing a planar layer using an ECMD technique and then applying an ECMP technique on the planar film in the same electrolyte by reversing the applied voltage. Alternately the ECMP step can be carried out in a separate machine and a different etching electrolyte or electropolishing solution. This way the thickness of the deposit may be reduced in a planar manner. In fact, an ECMP technique may be continued until all the metal on the field regions is removed. It should be noted that a WSID may or may not be used during the electroetching process since substantially planar etching can be achieved either way as long as the starting layer surface is planar.
FIG. 1 is a schematic illustration of an exemplary conventional ECMPR system 10 used for processing wafers. In FIG. 1, a WSID 12 having openings 14 in it, is disposed in close proximity of a workpiece or wafer 16 to be processed. The wafer 16 is a silicon wafer to be plated with a conductor metal, preferably copper or copper alloy. The wafer may or may not have a previously plated copper layer on it. The wafer 16 is retained by a wafer carrier 18 so as to position front surface 20 of the wafer against top surface 22 of the WSID 12. The openings 14 are designed to assure uniform deposition of copper from an electrolyte solution 24, depicted by arrows, onto the front surface 22, or uniform electropolishing from the front surface 22. The top surface 22 of the WSID 12 facing the front surface 20 of the wafer is used as the sweeper and the WSID 12 itself establishes appropriate electrolyte flow and electric field flow to the front surface 22 for globally uniform deposition or electroetching. Such an ECMPR system 10 also includes an electrode 26, which is immersed in the electrolyte 24. The electrolyte solution 24 is contained in a process chamber 25. The electrolyte 24 is in fluid communication with the electrode 26 and the front surface 20 of the wafer 16 through the openings 14 in the WSID 12.
It should be noted that the electrode 26 is only schematically shown in FIG. 1. In actual practice, the electrodes are shielded with a particle filter and other precautions are taken to avoid bubble accumulation under the WSID and to avoid particles generated on the electrode 26 to reach the surface of the wafer 16. An exemplary copper electrolyte may be copper sulfate solution with additives such as accelerators, suppressors, leveler, chloride and such, which are commonly used in the industry. The top surface 22 of the WSID 12 sweeps the front surface 20 the wafer while an electrical potential is established between the electrode 26 and the front surface 20 of the wafer. For deposition of a planar film such as copper, the front surface of the wafer 12 is made more cathodic (negative) compared to the electrode 26, which becomes the anode. For electropolishing in the same system the wafer surface is made more anodic than the electrode.
U.S. application Ser. No. 09/960,236 filed on Sep. 20, 2001, entitled “Mask Plate Design,” assigned to the assignee of the present invention, discloses various WSID embodiments. Also, U.S. application Ser. No. 10/155,828 filed on May 23, 2002, entitled Low Force Electrochemical Mechanical Deposition Method and Apparatus, also assigned to the same assignee of the present invention teaches means of applying force to the wafer surface by a WSID for ECMPR.
To this end, however, while these techniques assist in obtaining planar metal deposits or novel metal structures on workpieces and wafers, and other means of planar removal of materials from the wafer surfaces, there is still a need for further development of high-throughput approaches and apparatus that can yield deposits with better uniformity and high yield, and methods and apparatus that provide more uniform material removal from workpiece surfaces.